A 25% Duty -Cycle Clock Generation Circuit in 0.13 μ m CMOS

A 25% duty cycle clock generation circuit for wireless transceiver is designed in this paper, including divider based on current mode logic (CML) latch, the AND gates and buffers. The advantages and disadvantages of main structure and the principle of the clock generation circuit are analyzed. The key sub-circuits and layouts such as the divider-by-two, logic gates and buffers are designed based on 0.13μ m CMOS process. The simulation results show that the operating frequency range of the 25% duty cycle clock generation circuit is 0.02-2.5GHz, and the rise (fall) time is 0.02-ns.