A K-Band High-Linearity and Low-Noise Down-Conversion Mixer in 65nm CMOS

This paper presents a K-band down-conversion mixer in a 65nm CMOS process. To improve the conversion gain, linearity, bandwidth and noise Figure performance, instead of using the conventional Gilbert mixer, a transformer is introduced between the transconductance stage and the switching quad stage, realizing a radio-frequency (RF) common-source (CS) pre-amplifier and a current-mode passive mixer. With measurements, the down-conversion mixer achieves a conversion gain of 8 dB, a 3-dB bandwidth covering from 16 to 23 GHz, an input 1-dB compression point (IP1dB) of −8.3 dBm, an output 1-dB compression point (OP1dB) of −1.1 dBm and a noise Figure of 4.3 dB, while consuming 23-mW DC power consumption from a 1.2-V supply voltage.