A Low-Power Two-Step Time-to-Digital Conversion in 28 nm CMOS

In this paper, we propose a two-step time-to-digital converter (TDC) using gated delay technique to reduce power consumption. To reduce power consumption gated delay technology turns the delay chain off when the arbiter is not sampling. Simulation results show that the TDC resolution can reach 7ps when fabricated in 28 nm CMOS process, and the power consumption is reduced by 60% compared to the conventional two-step TDC.

I. Introduction

In recent years, all-digital phase-locked loops (ADPLLs) have been rapidly developed for RF and high-performance frequency synthesis due to the advantages of high integration and insensitivity to PVT. A typical ADPLL usually includes a digital control oscillator, a time-to-digital converter (TDC) and a frequency divider [1]. In the face of the times, the requirements for circuit performance are increasing, and one of the most challenging aspects of designing a low-noise, low-power, wideband fractional-division all-digital phase-locked loop is designing a TDC with wide dynamic range, high resolution, and low power consumption. in conventional delay-chain-based TDCs, wide dynamic range implies a long delay chain and large power consumption, and the resolution is proportional to the delay of the inverter and limited by the process.