A Novel High-Gain PAM4 Baud-Rate Phase Detector for ADC-Based CDR

In this letter, we propose a novel high-gain four-level pulse amplitude modulation (PAM4) baud-rate phase detector (BRPD) for the ADC-based high-speed clock and data recovery (CDR) circuit. The PAM4 phase decisions are generated by three adjacent data and three adjacent error types. In addition, a linear model of the proposed PAM4 BRPD is developed for the first time to precisely calculate the gain, which is also critical for analyzing the key characteristics of the PAM4 BRPD-based CDR. Moreover, such a CDR is designed with 12nm CMOS technology and supplied with 0.8 voltage. The transistor simulation results show that the CDR can operate at 112 Gb/s, the RMS jitter of the recovered clock is 523 fs, and the CDR’s jitter tolerance meets the CEI-112G-LR-PAM4 mask.