Implementation of High-Speed Hybrid Carry Select Adder using Binary to Excess-1 Converter

Adders are the basic building blocks in various digital signal processing applications such as convolution, correlation, and filters. However, conventional adders like ripple carry adders, carry-look-ahead adder, carry save adders were resulted in higher area, power, delay consumptions. Therefore, this work is focused on design and implementation of high-speed hybrid carry select adder (HCSLA) using binary to excess-1 converter (BEC). Initially, modified brent kung adder (MBKA) is developed, which is parallel prefix adder and exhibits the high-speed operations with low computational complexity. Further, MBKA is introduced in the first stage HCSLA. Then, BEC module is developed in the second stage of HCSLA and generates the sum. The simulation revealed that the proposed HCSLA-MBKA resulted in superior performance in terms of area, delay, power as compared to conventional adders.