FPGA Implementation of Raptor Coded DS-CDMA for Wireless Sensor Networks in Low SNR Regime

Reliable communications over a noisy channel have emerged as a severe challenge in the field of digital wireless communications. The proposed system addresses the high BER issue in AWGN channels in the Low SNR (LSNR) regime by combining the Raptor code with the DS-CDMA technique. This paper focuses on the hardware implementation of the proposed system. The hardware implementation was implemented on FPGA because it has the advantage of flexibility over traditional ASIC implementation. The Quarts tool is used to synthesize the proposed system on FPGA Altera DE2 70 using VHDL. As can be found in the report of compilation, approximately 32421 logic elements of the 68,416 logic elements available (47%) and 97 pins of the available 622 pins (16%) were employed.