Switching and Analog/RF performance improvement of Graded Channel Double Gate Junctionless FET: A Simulation Study

A graded-channel double gate junction less FET (GC-DG-JL-FET) is investigated in this paper, to improve switching and RF performance of the device. The channel-region of the proposed structure comprises of two non-overlapping materials. The first region is constructed using Silicon-Germanium
$(SiGe)$
, and the second is composed of Silicon (Si), having channel lengths
$L_{C1}$
and
$L_{C2}$
, respectively. The region wise uniform doping concentration profiles are used for this study, which are
$N_{d1}$
for region one and
$N_{d2}$
for region two. The Hafnium Oxide
$(HfO_{2})$
is used as gate oxide. The operation of the proposed device assessed using drain current
$(I_{ds})$
, trans-conductance
$(g_{m})$
, trans-conductance generation efficiency
$(g_{m}/I_{ds})$
, unity gain cutoff frequency
$(f_{t})$
. Further, for a fixed channel length (20 nm), the lengths of the two non-overlapping regions (i.e.
$L_{C1}$
and
$L_{C2}$
) of GC-DG-JLFET is optimized using 2D-simulations to analyze the effect of the variation in the RF -performance of the structure. It is noted, an increment in
$L_{C1}$
improves electrostatic control of the gate under the OFF state which enhances the RF characteristics of the proposed device. When optimized, the GC-DG-JL-FET for
$L_{C1}=15$
nm offers a peak
$g_{m}$
and
$f_{t}$
of 1580
$\mu S/\mu m$
and 470 GHz, respectively for a total channel length of 20 nm. On account of such results, the GC-DG-JL-FET device structure can be an apropos choice for analog/RF applications.