Low Power Optimization of Full Adder using GNRFET Technology– A Review

This review paper illustrates the advantages of GNRFETs and their use in adder circuits to reduce interconnect and improve delay, power dissipation, and speed. Future nanotechnology will have to deal with CMOS limitations such as DIBL, short channel effect, high leakage current, and temperature-dependent threshold voltage. Graphene nanoribbon FET solves these problems. Because its channel is formed by graphene ribbons, graphene nanoribbon FETs have replaced CMOS. Several studies are currently underway to develop and examine the application of graphene nanoribbon FET in half and full adders. A comparison study for half and full adders using graphene nanoribbon FETs is presented in this article, with parameters like propagation delay, power dissipation, and PDP being studied. In comparison to CMOS logic, graphene nanoribbon FET-based digital circuits are substantially more efficient. We are expecting 99%, 85%, 97% and 87% reduction in power consumption, delay, Power delay product and leakage power respectively. HSPICE software is used to simulate the performance parameters and results.