A Low Delay AES Round Transform Architecture Using Constant Matrix Multiplications Merging Technologies

This paper presents a low delay architecture design method for the hardware implementation of the Advanced Encryption Standard (AES) algorithm. The proposed architecture is designed by using constant matrix multiplications (CMM) merging technologies. To reduce the area cost in hardware implementations, S-box/InvS-box is usually implemented with composite field arithmetic (CFA) technologies. In this paper, CMM in CFA-based S-box/InvS-box are further merged with constant coefficient multiplications in MixColumns/ InvMixColumns, which can also be expressed as CMM forms. By the merging, the delay of the hardware implementation of encryption round transform is reduced at the cost of slight area cost increasing, and both delay and area cost are reduced in hardware implementations of decryption round transform. Hardware complexities analysis indicates that our designs have less delay compared with previous works.