A 25ns 16K CMOS PROM using a 4-transistor cell

A 25ns, 250mW, 2K×8 PROM using 1.2μ N-well CMOS technology will be described. Speed and programmability have been optimized by separating read and write transistors in a 4-transistor differential cell. A substrate bias generator raises the latchup immunity to over 200mA.