P-channel, vertical insulated gate bipolar transistors with collector short

P-channel, collector-shorted, vertical insulated gate bipolar transistors with hexagonal and square cell geometries were studied. The presence of the collector short, surrounding the edges of the device, resulted in a linear I-V region before the conductivity modulation region sets in. The effect of poly-Si overlap and JFET dosage on forward drop and breakdown voltage were analyzed for hexagonal and square DMOS cell geometries. In contrast to the conventional IGBT, the turn-off time increases with increasing collector current A maximum controllable current of -5A (-710A/cm
²
was measured when switching into -300V at room temperature. The built-in anti-parallel diode formed between the collector short and the deep n+ short in the DMOS cells has also been character ized.