New degradation phenomena by source and drain hot-carriers in half-micron P-MOSFETs

Hot-carrier phenomena in half-micron offset type P-MOSFETs have been investigated, comparing to that of conventional ones with the same effective channel length. At high gate bias stress test, it is newly found that injected source hot-holes cause large minus V
th
shift in the forward mode measurement. In addition, in the drain region, double injections of hot-electron and hot-hole occurs. As a result, V
th
shift in the reverse mode changes from plus to minus with stress time. As source hot-holes are considered to affect the reliability of actual CMOS circuits, it as important to introduce the LDD structure into half-micron P-MOSFETs to reduce the high electric field in the source region.