A high performance submicron CMOS process with self-aligned chan-stop and punch-through implants (Twin-Tub V)

An optimally designed process used for our fifth generation CMOS technology (Twin-Tub V) is described in this paper. This process has the inherent advantages of process simplicity, excellent transistor performance and latch-up resistance. A single level silicide and two level metal interconnect is also incorporated in this technology.