Abstract:
Presented are the results of a merged CMOS/bipolar process used to implement circuit structures using both fully isolated bipolar transistors with low collector series re...Show MoreMetadata
Abstract:
Presented are the results of a merged CMOS/bipolar process used to implement circuit structures using both fully isolated bipolar transistors with low collector series resistance and CMOS transistors. Latch-up suppression and effective bipolar performance are simultaneously achieved by the combined use of an n+ buried layer, epitaxial processing and a tailored base ion implant. A merged CMOS/bipolar buffer circuit is described and measured results are shown.
Published in: 1983 International Electron Devices Meeting
Date of Conference: 05-07 December 1983
Date Added to IEEE Xplore: 09 August 2005