Optimization of depletion-mode MOSFET's

Depletion-mode MOSFET's used as load devices in NMOS logic circuits are characterized and optimized. The dependence of V
T
, transconductance, load efficiency and short-channel effects on the device geometries, channel profiles, and mode of operation are discussed. Based on the improved understanding, simple models are used with carefully selected parameters to optimize the inverter circuit performance. The dependence of inverter delay on the V
T
of the load device is studied, and it is found that a less negative V
T
is desirable for a smaller chip area and smaller delay.