Characterization of two step impact ionization and its influence in NMOS and PMOS VLSI's

Two step impact ionization phenomena near the high electric field drain region are characterized, both theoretically and experimentally, in small geometry NMOS and PMOS structures. Influences of primary and secondary impact ionized carrier flows are quantitatively considered as design constraints in high density MOS memories, more specifically for CMOS devices and also for poly-Si resistor load RAM cells.