High performance, high density MOS process using polyimide interlevel insulation

High performance, high density scaled MOS processes have been developed by reducing parasitic lead capacitances and resistances through the use of MoSi
2
gates and polyimide as interlevel dielectric insulator. The self-aligned gates were passivated using dual layer of doped oxide and DuPont PI2545 polyamic resin 1.7 micron thick reducing interlevel capacitance to 2.66×10
^-9
farads/cm
²
, half that of conventional doped oxide. The speed power products estimated from 25 stage ring oscillator with 2 micron gates on 600Å gate oxides show minimum delays of 500 psec/gate and minimum speed power product of 120 femto joules at lower currents.