The cross charge-control flip-flop: a low-power and high-speed flip-flop suitable for mobile application SoCs

This paper presents a low power and high-speed flip-flop named cross charge-control flip-flop (XCFF). It has two dynamic nodes driving output transistors separately. The minimum power-delay product of the XCFF is 48% smaller than that of CMOS flip-flop and 20% smaller than that of the semi-dynamic flip-flop (SDFF). Applying it to a 125-MHz microprocessor core, we can achieve 10% power reduction without any speed or area penalty.