A highly manufacturable MIPS (metal inserted poly-Si stack) technology with novel threshold voltage control

The novel technique to control the V/sub th/ of n/pMOS for HfSiO(N) in both poly-Si and MIPS (metal inserted poly-Si stack) gates is demonstrated. By adding AlO/sub x/ on HfSiO prior to poly-Si deposition, we successfully achieve symmetrical V/sub th/, values of 0.52V (nMOS), /-0.51V (pMOS) and high performance as I/sub on/, of 423uA/um for nMOS and 207uA/um for pMOS at I/sub off/=20pA/um. In addition, we find out that the ultra-thin and conformal TaN layer in MIPS gate does not contribute to the gate work function. By optimizing the TaN thickness, similar V/sub th/ values, compared to poly-Si gate, are achieved. Consequently, the measured saturation currents at I/sub off/=20pA/um are 430uA/um for nMOS and 250uA/um for pMOS. Both issues of PBTI for HfSiO/AlO/sub x//poly-Si structure and NBTI for HfSiO/AlO/sub x//MIPS structure are resolved by optimizing the post deposition annealing condition and using ozone interfacial oxide, respectively.