An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC

In this paper, we present an efficient architecture for deblocking filter in H.264/AVC. A novel 2-dimensional parallel memory scheme is employed in order to achieve highly efficient parallel access in both horizontal and vertical directions. By using this parallel memory scheme, we also eliminate the need for a transpose circuit. Our design is implemented under 0.35/spl mu/m technology. Synthesis results show that the equivalent gate count is only 9.35K (not including SRAMs) when the maximum frequency is 100MHz.