Wafer bonding of damascene-patterned metal/adhesive redistribution layers for via-first three-dimensional (3D) interconnect

A novel via-first, back-end-of-the-line (BEOL) compatible, monolithic wafer-level three-dimensional (3D) integration technology platform is being developed, which employs wafer bonding of damascene-patterned metal/adhesive redistribution layers on two wafers, thus facilitating both high density of inter-wafer electrical interconnects and strong adhesive bond of two wafers in one unit processing step. Two key steps for this approach are 1) fabrication of a metal/adhesive redistribution layer on the top of the BEOL-processed wafer by damascene patterning and 2) face-to-face alignment and bonding of two wafers utilizing the metal/adhesive redistribution layers. Repeating a whole 3D process flow, the third wafer (or more) can then be added. Copper/tantalum (Cu/Ta) and benzocyclobutene (BCB) are selected as the metal and adhesive for the feasibility demonstration of the via-first 3D approach. Critical processing challenges are investigated, including: 1) BCB partial curing and patterning; 2) Ta and Cu deposition; 3) Cu/BCB chemical mechanical planarization (CMP); 4) post-CMP treatment; and 5) bonding process parameters. Wet chemical and dry plasma surface preparation techniques are used for post-CMP treatment and pre-bonding surface preparation, a critical step in facilitating a strong, reliable bond between BCB-to-BCB regions as well as a low contact resistance between Cu-to-Cu regions. Results on blanket BCB/Si wafers show a strong BCB-to-BCB bond with mean critical adhesion energy in a range of 14-31 J/m . For patterned Cu/BCB wafers, interfaces of bonded BCB-to-BCB, Cu-to-Cu, and BCB-to-Cu areas are imaged by focused ion beam scanning electron microscopy (FIB/SEM), showing the feasibility of these bonds. Specific contact resistance of the Cu-to-Cu interconnect is on the order of 1 /spl times/ 10/sup -7/ /spl Omega/-cm/sup 2/, a promising preliminary result indicating electrical contact is possible using this new 3D technology platform.

Introduction

Three-dimensional (3D) integration technology holds promise for reducing interconnect delays in future integrated circuits (ICs) by reducing length and number of long interconnect lines [1]–[3] as well as offering heterogeneous integration of processes and devices through die-to-die, die-to-wafer, or wafer-to-wafer approaches [4]–[6]. Of these approaches, monolithic wafer-level processing also holds promise for decreasing cost through parallel fabrication methods for high volume manufacturing. Various wafer-level approaches have been demonstrated [1]–[3], with each approach having its own advantages. For example, the dielectric bonding technology platform offers a robust bonding process [1], the handle wafer process offers simple alignment capability [2], and the copper bonding technology platform offers a means for simple electrical interconnect [3]. For the integration of fully fabricated wafers in a packaging facility, the capabilities offered by both the dielectric bonding and copper bonding approaches are clearly critical. Furthermore, the ability to easily fabricate a general redistribution layer for routing of signals between generic ICs is also needed.