Introduction
Three-dimensional (3D) integration technology holds promise for reducing interconnect delays in future integrated circuits (ICs) by reducing length and number of long interconnect lines [1]–[3] as well as offering heterogeneous integration of processes and devices through die-to-die, die-to-wafer, or wafer-to-wafer approaches [4]–[6]. Of these approaches, monolithic wafer-level processing also holds promise for decreasing cost through parallel fabrication methods for high volume manufacturing. Various wafer-level approaches have been demonstrated [1]–[3], with each approach having its own advantages. For example, the dielectric bonding technology platform offers a robust bonding process [1], the handle wafer process offers simple alignment capability [2], and the copper bonding technology platform offers a means for simple electrical interconnect [3]. For the integration of fully fabricated wafers in a packaging facility, the capabilities offered by both the dielectric bonding and copper bonding approaches are clearly critical. Furthermore, the ability to easily fabricate a general redistribution layer for routing of signals between generic ICs is also needed.