A low voltage high unity-gain bandwidth CMOS op-amp

This work presents a /spl plusmn/1V CMOS operation amplifier with constant-g/sub m/ rail-to-rail input stage and class-AB output stage. The designed op-amp has been implemented in TSMC 2P4M 0.35 /spl mu/m CMOS technology and simulated by Hspice. The unity-gain bandwidth of the op-amp is 13.1 MHz with Miller compensation. The slew-rate and settling time are 24V//spl mu/s and 0.48 /spl mu/s, respectively. The open loop gain is 108 dB with 58 degree phase margin.