Fault tree analysis of embedded systems using SystemC

System fault-tree analysis is a technique for modeling dependability that is in widespread use. For systems such as embedded systems that include both hardware and software, the integration of hardware and software fault trees has proved problematic. In this paper, we present a method for reliability and safety analysis of embedded systems modeled by SystemC language. The evaluation is based on the fault trees generated from both hardware and software parts of the embedded systems described in the unified language. The unified modeling of both hardware and software of embedded systems using SystemC enables designers to be early aware from the safety and reliability of their designs more accurate than that of considering them apart.