I. Introduction
High frequency on-wafer measurements of single transistors, simple circuits, and transmission line structures are critical to characterization and development of advanced integrated circuit technologies. Although there exist many possible calibration and de-embedding methods, each has its drawbacks. Although on-wafer calibrations may be performed (TRL, LRM, LRRM, etc.) [1], [3], these require a number of precisely designed, fabricated, and verified calibration structures which consume significant amounts of expensive wafer real estate and which may not be trivial to reproduce at the desired level of precision, particularly in advanced and emerging integrated circuit processes in which process steps may be intentionally (or unintentionally) varied in order to explore design space.