Embedded test for a new memory-card architecture

Requirements for a new Cray Inc. computer system mean that the system's memory cards have high-speed SerDes interfaces and multiple memory controllers in a semicustom IC close to the memory chips. As a result, the functionality of a card is much greater than is current practice, and the cards can not be connected to existing memory testers. An embedded test system is designed for the card that can test all aspects of the card including the SerDes paths, a large L3 cache, the memory controllers, and the memory parts mounted on the cards, with testing driven from a JTAG port. The test capability is based in a microcoded controller, with data packets being generated and checked rather than directly controlling the logic being exercised. Some of the test implementation discussed here is patent pending.