Revisiting VLSI interconnects in deep sub-micron: some open questions

Deep sub-micron technology has increased the design complexity of VLSI circuits. Design of routers now has to take care of the timing issues for faster design convergence. This has yielded wider scope of research in design and performance of interconnects. We focus on certain critical aspects of interconnects, and related open research issues. The discussions are on (i) the fidelity of delay estimators, and its use in finding global routing trees, (ii) a new class of routing trees, and (in) the evolution of new metric for interconnect performance measurement.