Contents 1. Introduction
Low-voltage high-density embedded RAMs (e-RAMs) are becoming increasingly important because they play critical roles in reducing power dissipation and chip size of MPU/MCU/SoC for power-aware systems. Thus, research and development [1]–[6] aiming at sub-1-V RAMs has been active, as exemplified by the presentation of a 0.6-V 16-Mb e-DRAM [5]. To create such e-RAMs, however, many challenges remain with RAM cells and peripheral circuits [1], [2]: For RAM cells, in addition to being the smallest and simplest cell possible, signal-to-noise ratio (S/N) must be maintained high to ensure stable and reliable operations because the ratio is always worsened at low voltages as the signal charge of non-selected cells and the signal voltage developed on the data (bit) line decrease. It is also worsened when leakage in a cell increases. The traditional six-transistor (6-T) SRAM cell is well known to suffer from its large size, large soft-error rate (SER), and narrow static noise margin even at about 1.2V. This poses the difficult question of what makes for the best alternative. In the meantime, non-volatile RAMs are emerging as candidates. For peripheral circuits, both leakage and speed variations must be reduced [1], [2] because they are prominent at a lower voltage even for a fixed design parameter variation. Unfortunately, the parameter variations are more enhanced as the devices are scaled. Thus, in addition to new devices such as a fully-depleted (FD) SOI [7] and high-k gate insulators, a variety of solutions such as raising the threshold voltage of MOST and controlling internal power-supply voltages [1], [2] have been proposed to cope with the issues.
