Digital pulse width modulator architectures

This paper presents a survey and classification of architectures for integrated circuit implementation of digital pulse-width modulators (DPWM) targeting digital control of high-frequency switching DC-DC power converters. Previously presented designs are identified as particular cases of the proposed classification. In order to optimize circuit resources in terms of occupied area and power consumption, a general architecture based on tapped delay lines is proposed, which includes segmentation of the input digital code to drive binary weighted delay cells and thermometer-decoded unary delay cells. Integrated circuit design of a particular example of the segmented DPWM is described. The segmented DPWM prototype chip operates at 1 MHz switching frequency and has low power consumption and very small silicon area (0.07 mm/sup 2/ in a standard 0.5 micron CMOS process). Experimental results validate the functionality of the proposed segmented DPWM.

I. Introduction

Feasibility of practical high-frequency, high-performance digital controllers for DC-DC applications has recently been demonstrated [1]–[3]. Based on custom architectures and microelectronic realizations of the key building blocks, including high-resolution high-frequency digital pulse-width modulators (DPWM), simplified discrete-time compensator schemes, and A/D converters, such controllers can offer the advantages of lower sensitivity to parameter variations, programmability, and reduction or elimination of external passive components, without compromising dynamic performance, simplicity or cost.