3D interconnection and packaging: impending reality or still a dream?

Traditional interconnect schemes are basically two-dimensional. It has long been a dream for system designers to be able to combine multiple integrated circuits by connecting them in the third dimension. Three approaches to the 3D interconnect problem are described: system in a package (3D-SiP), system on a chip (3D-SoC) and 3D integrated circuits (3D-IC).

As integrated circuit technology continuously improves its integration capabilities, and SoC is a possibility, the limitations of 2D-inter-connects are more obvious. Integrated circuits are partioned in function blocks (“tiles”) that are interconnected using routing in parallel planes (2D). With the scaling of the technology, these long lines have become the speed-limiting factor on the chip, as well as a significant source for power consumption. If the functional “tiles” on the chip could be stacked in three dimensions, the chip area would be reduced and much shorter interconnects between would result.