An ADPLL circuit using a DDPS for genlock applications

This paper presents a fully programmable All-Digital PLL (ADPLL) circuit that is able to synchronize any frequency between 12 MHz and 200 MHz, with a frequency between 24 Hz and 100 MHz. This ADPLL circuit uses a Direct Digital Period Synthesizer as a digitally controlled oscillator. The measured jitter at the output is between 184 and 274 ps (depending on control parameters). The circuit is implemented in 0.18 /spl mu/m CMOS technology and dissipates 50 mW when running at 150 MHz.