Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models

Interconnects constitute a dominant source of circuit delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this paper, a practical interconnect delay and slew analysis technique is presented to facilitate efficient evaluation of wire performance variability. By harnessing a collection of computationally efficient procedures and closed-form formulas, process variations are directly mapped into the variability of the output delay and slew. An efficient method based on sensitivity analysis is implemented to calculate driving point models under variations for gate-level timing analysis. The proposed adjoint technique not only provides statistical performance variations of the interconnect network under analysis, but also produces delay and slew expressions parameterized in the underlying process variations in a quadratic parametric form. As such, it can be harnessed to enable statistical timing analysis while considering important statistical correlations. Our experimental results have indicated that the presented analysis is accurate regardless of location of sink nodes and it is also robust over a wide range of process variations.

I. Introduction

Interconnect parasitics are the dominant source of on-chip circuit delays for modern VLSI technologies. To efficiently account for wire delays in the design process, interconnect modeling, particularly the model order reduction of passive linear networks, has been an active topic of research in computer-aided design (CAD) community for more than a decade (e.g., [1]–[4]). As modern VLSI technologies approach the nanoscale manufacturing regime, it is becoming increasingly difficult to control systematic/random fluctuations introduced in the fabrication process, leading to growing variations in the critical dimensions and material properties of metal and dielectric layers [5], [6]. These process variations inevitably introduce performance variations in interconnects, which must be fully accounted for during timing verification. In the past, a significant amount of work has emerged to address interconnect variability via various avenues through variational interconnect model order reduction [7]–[13], or via statistical/variational interconnect analysis [11], [14], [15].