I. Introduction
The International Technology Roadmap for Semiconductors (ITRS) [29] projects that it will soon be feasible to design multibillion transistor chips. Increasing design complexity and diminishing returns from uniprocessor optimizations have led to the emergence of multicore architectures in the form of multiprocessor systems-on-a-chip (MPSoCs) and chip multiprocessors (CMPs). The growing number of on-chip resources in combination with the diverse range of current and future applications that these parallel systems are to run are sparking a widening design space of multicore architecture implementations. Architects and designers are, therefore, faced with the tough challenge of selecting the most suitable parallel system design that will best balance their application requirements in terms of the anticipated cost-benefits.