I. Introduction
THIS Paper describes a new model for the change in buffer delay caused by both power and ground supply level variations and level variations between stages in sequences of repeaters. These delay changes are a large component of the total timing jitter for a signal where the jitter accounts for all noise sources such as substrate noise, and coupling noise, as well as power level noise. There is a substantial amount of previous work in this area, notably papers [4], [6], [13], [14], and [19]. However, for several reasons described below, we believe that the problem bears reexamination and a renewed effort to create a fast, simple model suitable for mass implementation in a modern design flow.