Noise-aware interconnect power optimization in domino logic synthesis

Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultradeep submicrometer processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized, which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption about 14% on average.

I. Introduction

The era of system-on-a-chip integrated with millions of transistors drives the technology to scale down to ultradeep submicrometer (UDSM) range, 0.25 or below. As feature size decreases, interconnect pitch also shrinks while packaging is becoming denser. Meanwhile, wire aspect ratio (namely, metal height/width) increases from 1.8 in 0.18- processes to 2.7 in 0.07- processes to keep resistance in control for high performance, as shown in Table I [35]. These apparent trends bring up two competitive issues: power efficiency and noise immunity on interconnects. TABLE I International Technology Roadmap for Semiconductors

Year	1997	1999	2002	2005	2008
Process (nm)	250	180	130	100	70
Frequency (MHz)	750	1250	2100	3500	6000
Wiring layers	6	6–7	7	7–8	.
Min wire pitch (nm)	640	460	340	260	190
Wire aspect ratio	1.8	1.8	2.1	2.4	2.7
MPU TRs (106)	11	21	76	200	520
Area (mm2)	300	340	430	520	620
Max power (W)	70	90	130	160	170

Fig. 1. Cross-coupling capacitance as a dominant factor in nanometer technology.