Leakage control techniques for designing robust, low power wide-OR domino logic for sub-130nm CMOS technologies

In this paper, we discuss the design of leakage tolerant wide-OR domino gates for deep submicron (DSM), bulk CMOS technologies. Technology scaling is resulting in 3-5x increase in transistor I/sub OFF///spl mu/m per generation resulting in 15%-30% noise margin degradation of high performance domino gates. We investigate several techniques that can improve the noise margin of domino logic gates and thereby ensure their reliable operation for sub-130nm technologies. Our simulations indicate that, selective usage of dual V/sub TH/ transistors shows acceptable energy-delay tradeoffs for the 90nm technology. However, techniques like supply voltage (V/sub cc/) reduction and using non-minimum L/sub c/ transistors are required in order to ensure robust and scalable wide-OR domino designs for the 70nm generation.