An Efficient Optimization Based Method to Evaluate the DRV of SRAM Cells

To reduce the substantial leakage current, the supply voltage of SRAM cells has being scaled down towards its lower limit, which is called the data Retention Voltage (DRV). Although the power consumption is largely reduced, this down-scaling trend, however, impacts the stability of the SRAM cell due to the unpredictable process or device parameter variations. In this work, we propose a novel method to evaluate the DRV of SRAM cells at the presence of variations. The DRV issue is first formulated as a time domain worst performance bound problem. To accurately and efficiently evaluate the DRV, a multi-start point (MSP) optimization strategy is then studied and developed with the use of practical circuit simulator. One feature of the proposed method is that it can efficiently evaluate the DRV without suffering from any process/model accuracy. Experiment results show that it achieves a speedup of 3 and 5-7 order over the Importance Sampling (IS) and Monte Carlo (MC) method respectively under the context of the DRV evaluation in this paper. The proposed method can serve as an efficient DRV evaluation tool on any specific technology process or in-house circuit simulator. In this work, the DRVs at the technology node from 130 nm to 45 nm under the influence of different variation sources are also presented and analyzed.

I. Introduction

Leakage current, nowadays, is the dominant power dissipation source in the large SRAM cell array. Driven by the intensive low power application demand, how to suppress the leakage current has been a critical topic for the memory designers during the past decade. One of the most effective ways for leakage current suppression in the SRAM cell array is to reduce the supply voltage (Vdd) [3]. This method, however, sacrifices the robustness of the SRAM cell since the data stored at the internal node will degrade as the supply voltage decreases. On the other hand, the variations of process or device parameters put a further challenge to the reliability of SRAM cell design [2]. One of the known variation sources in the SRAM cell is the threshold voltage mismatch due to the random fluctuation of the dopant atoms in the device channel [1] which is called Random Dopant Fluctuation (RDF). Since this random variation is inversely proportional to the device area, it manifests itself significantly in the large SRAM cell array where minimum geometry size is usually adopted in order to achieve a high density occupation. in addition, some other sources such as the geometry variations in transistor width and channel length introduced from the manufacture process and the fluctuation of temperature cannot be ignored. These unpredictable parameter variations will break the internal balance of SRAM cells and deteriorate the stored data. The minimum supply voltage to keep a correct data stored in the SRAM cell at the presence of variations is called Data Retention Voltage (DRV) [3]. Accurate estimation of the DRV is a critical demand for both robust and low power design.