A Reconfigurable and Power-Scalable 10–12 Bit 0.4–44 MS/s Pipelined ADC With 0.35–0.5 pJ/Step in 1.2 V 90 nm Digital CMOS

A pipelined ADC, reconfigurable over bandwidths of 0.2-22 MHz (sampling frequencies of 0.4-44 MS/s) and resolutions of 10-12 bits, is described for applications in multi-standard wireless terminals. Fabricated in a 1.2-V 90-nm digital CMOS technology, this ADC achieves low power (figure-of-merit of FOM=0.35 to 0.5 pJ per A/D conversion step) over its full bandwidth-resolution range. Accordingly, compared to state-of-the-art power-efficient reconfigurable pipelined ADCs, this ADC provides a larger bandwidth-resolution reconfigurability space, while maintaining a highly competitive FOM over this entire space. To achieve such low-power performance in a low-voltage nanometer CMOS process, this work utilizes: (1) a current-scalable frequency-compensation technique to design low-power current-scalable two-stage opamps; (2) a switched-capacitor technique to design dynamic comparators with low input capacitance (input-loading effect); and (3) a low-power digital background gain-calibration technique. The large bandwidth and resolution reconfigurability ranges are achieved using current-scaling and stage-bypass techniques, respectively.

I. Introduction

The growing demand for multi-standard wireless terminals is fueling interest in analog-to-digital converters (ADCs) that are reconfigurable over a wide range of bandwidths BW and resolutions , while having a power dissipation that scales with both bandwidth and resolution, and hence a constant figure-of-merit (FOM). Such ADCs must be implemented in a standard digital CMOS process, for higher integration of the analog and digital functions in a communication system and for lower fabrication costs. However, in nanometer CMOS technologies, the decreasing supply voltages and the shrinking devices with poor analog-signal-processing capabilities complicate the design of low-power ADCs.