A 6.0–13.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS

A 6.0-13.5 GHz alias-locked loop (ALL) frequency synthesizer is designed and simulated in 130 nm CMOS. Using an aliasing divider, the ALL architecture makes it possible to create high-speed frequency synthesis circuits without relying on a traditional divider clocked at fVCO in the feedback path. In this implementation, a new architecture of high frequency ring oscillator is proposed with a feedforward path and selectable modes of operation for different frequency ranges. This ring oscillator provides both a high oscillating frequency and a wide tuning range. Simulation results have shown that the design synthesizes the desired frequencies and consumes 30.01 mW @ 13.0 GHz with a 1.2 V power supply.

I. Introduction

The phase-locked loop (PLL) is a critical component in many circuits and systems as it provides the timing basis for functions such as clock control, data recovery, and synchronization. With the fast development of radio frequency and millimeter wave communications, high frequency synthesizers have become more important in recent years. A 410 GHz CMOS Push-Push oscillator has already been demonstrated [1]. In a traditional PLL implementation, a divider in the feedback path converts higher frequencies to lower frequencies. Unfortunately, a traditional divider in PLL is based on flip-flops and will not work at such high frequencies. Designers usually resort to regenerative dividers [2] or injection locked dividers [3] to extend the operating frequency of their devices. However, both injection locked dividers and regenerative dividers typically rely on shunt peaking inductors that cost large areas and have limited tuning range.