I. Introduction
Multi-Threshold CMOS (MTCMOS) technology [1], [2], also frequently referred to as power-gating, is a widely used technique for reducing leakage power during standby (or sleep) mode while still permitting high-speed operation during active mode in burst mode type circuits [3]. Failure to control leakage in such circuits with long idle periods can greatly reduce the battery lifetime [4]. Although it is effective in reducing sleep-mode power consumption, the power-gating circuit introduces several overheads in terms of the performance, area, dynamic power dissipation and signal integrity. For example, the use of a header sleep transistor causes the virtual power supply rail to discharge to a steady-state value close to ground if the sleep period is sufficiently long. This suppresses the leakage currents effectively due to the near-zero difference between the circuit's power supply and ground. However, when the virtual power supply is restored to its full-swing value during the transition from sleep to active mode, there is a large power-on current-rush through the sleep transistor [5], [6]. Besides wasting energy and increasing the wake-up time, these current surges also cause voltage fluctuations in the power/ground network due to the parasitic impedances of the off-chip bonding wires and the on-chip power rails. The IR-drop and Ldi/dt during the wake-up process, collectively referred to as the power gating noise (PGN), can induce logic errors, increase the critical path delay of neighboring on-state circuits and affect the power plane integrity in low-power SoCs implemented in deeply scaled technologies which have narrow noise margins [4], [5]. Detailed studies on PGN in different power-gated MTCMOS combinational and sequential circuits have been recently reported in [4] and [7] respectively.