I. Introduction
Since digitally controlled RF technologies [1] can eliminate large on-chip passive devices and do not suffer from low supply-voltage operation, these technologies are attractive for reducing the transceiver die size with low power consumption. The all-digital phase locked loop (ADPLL) is the one of the most challenging blocks, because it is very difficult to achieve the low phase noise required in modern wireless systems for higher order modulation with low power consumption. Since phase noise is dominated by the quantization noise of the time-to-digital converter (TDC), and noise is limited by the inverter delay that can be achieved with the technology in use, recent work has utilized fine gate-length CMOS inverters [2]–[4]. However, fine gate-length inverters have large delay variations due to threshold-voltage fluctuations. The delay variations in the inverter chain produce additional quantization noise in TDC [3], [11], [14], [15], and the noise is cumulative when the signal propagates in the delay chain. A TDC utilizing vernier delay lines inherently has high time resolution, but this configuration requires a large number of vernier stages especially at low DCO frequency [14]–[16], and thus the cumulative quantization error becomes serious. Even though a TDC having a coarse and fine time quantization circuit, which can reduce the number of vernier stages [5]–[8], [23], [24], suffers from the quantization error due to gate-delay fluctuations. To reduce the noise in TDC, it is very important that we know how gate-delay fluctuations affect quantization noise.