I. Introduction
Charge-Pump based phase-locked loops (CPLL) are widely used as clock generators in a variety of applications including microprocessors, wireless receivers, serial link transceivers, and disk drive electronics [1]–[8]. One of the main reasons for the widely adopted use of the CPLL in most PLL systems is because it provides the theoretical zero static phase offset, and arguably one of the simplest and most effective design platforms. The CPLL also provides flexible design tradeoffs by decoupling various design parameters such as the loop bandwidth, damping factor, and lock range. While there are numerous CPLL design examples in the literature, precise analysis Third-order CPLL block diagram. and a mathematical clarity of the loop dynamics of the CPLL is lacking. The two most popular references in this arena by Hein and Scott [9] and Gardner [10] provide useful insight and analysis for second-order PLLs. Several other references [11], [12], provide simplified yet useful approximations of third-order CPLLs. However, they do not provide a complete and extensive analysis for practical integrated circuit (IC) PLLs, i.e., third-order CPLLs. The intent of this paper is to clarify and provide mathematically exact and insightful understanding of the PLL dynamics and accurate transfer functions of a practical CPLL system. The focus of the detailed derivations and analysis is on the CPLL example because IC designers predominantly choose CPLLs over other PLL architectures. Although the presentation is for a CPLL, the analysis can be readily extended for other PLL systems.