BiST model for IC RF-transceiver front-end

In this paper, a BiST technique for an RF transceiver front-end is presented. The test is aimed at spot defects typical of mass production in the CMOS process. The loop-back approach is used to detect faults modeled as resistive breaks or bridges. The resulting impairment in gain, noise figure or selectivity of the RF blocks are considered functional-level faults, and as such are subjected to test with PRBS stimulus and BER as the response at base-band. The extra test circuitry is limited and the on-chip resources are used to set-up the BiST. A model of a GSM transceiver with BiST is investigated to verify the proposed approach.

1. Introduction

Standard tests for present mixed-signal ICs are complex and usually comprise advanced measurements aimed at the relevant specifications. High performance instrumentation is essential to accomplish this task, and in case of a high volume production very expensive automatic test equipment (ATE) is indispensable [1]. To enhance the test throughput the need for performing parallel test even more boosts the test equipment costs. On the other hand, the advancing complexity and performance of present ICs, such as RF transceivers, are pushing the ATE to the edge of its limits. The standard tests driven by specifications are more and more difficult and time consuming. Additionally, the costly ATE still lags by one generation behind the new ICs to be tested.