Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 /spl mu/m technologies

We developed standard cell libraries for three technologies (0.13, 0.18 and 0.35 /spl mu/m) using an automatic layout generation tool that we have developed. The developed libraries are as competitive as manually-designed libraries in layout density and speed. We verify the functionalities of all cells and the speed of basic combinational cells on fabricated chips. The libraries are currently public to educational organizations in Japan.