Jitter analysis of a PLL-based CDR with a bang-bang phase detector

This paper provides a timing model to analyze the jitter generation of a bang-bang phase detector for PLL-based clock and data recovery (CDR) applications. Such a CDR is needed in the implementation of the serial data receiver in a broadband transceiver system. The input data is in Non-Return to Zero (NRZ) format. SPICE simulations are used to validate the analysis with particular emphasis on jitter generation caused by the bang-bang phase detector parameters.