Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance

A new approach is presented aimed at modeling mechanical stress effects which impact MOSFET electrical behavior. It is successful in accounting for mobility variations experimentally evidenced on complex MOSFET geometries. The newly developed mobility model proves to be an efficient way to include mechanical stress effects into standard simulation models. We show that stress effects can and should be taken into account in the IC design phase in present and sub 90 nm nodes CMOS generations.

Introduction

CMOS devices down scaling demands an increasing complexity in modeling to take into account new effects impacting MOSFET electrical behavior due to the ever increasing density of integration. Shallow Trench Isolation (STI) induced mechanical stress is the dominant source of mechanical stress variations in MOSFET channel following MOSFET geometry variations, such as Active Area (AA) size & shape, gate location inside AA. etc. It may account for more than mobility variations (see Figure 1).