On-chip segmented bus: a self-timed approach [SOC]

Bus structure is one of the important issues within the present day system-on-chip design paradigm. Speed and power consumption characteristics of a bus-based device are highly dependent on the bus organization. We propose a segmented bus architecture which shows potential for improving both speed and power related figures of a bus-based system. From a globally asynchronous locally synchronous systems perspective, self-timed logic seems appropriate for interconnecting sub-systems operating at different speeds. Hence, inter-module control follows self-timed design rules, whereas modules themselves can be synchronous entities.

1 Introduction

Modern deep sub-micron silicon technologies have given a real boost to system-on-a-chip (SOC) design research and development. The growing diversity of devices brings up an immense number of possible interfaces. In many situations, both the system design and performance are limited by the complexity of the interconnection between the different modules and blocks that are integrated into those chips. Furthermore, different data transfer speeds are required as well as parallel transmission. A simple bus is one such structure that may not be suitable for such a design. This is because only one module can transmit at a time and the bus is slow due to large capacitive load [6] caused by the interfaces of the modules that are attached to it and the long physical length.