A low-complexity combinatorial RNS multiplier

A novel very large scale integration architecture and the corresponding design methodology for a combinatorial adder-based residue number system (RNS) multiplier are presented in this paper. The proposed approach to residue multiplier design, exploits the nonoccurring combinations of input bits to reduce the number of 1-bit full adders (FAs) required to compose an RNS multiplier. In particular, input bits which cannot be simultaneously asserted for any input residue value are organized into couples or triplets, which can be processed by OR gates instead of 1-bit adders, therefore reducing the RNS multiplier complexity. By comparing the performance and hardware complexity of the proposed residue multiplier to previously reported designs, it is found that the introduced architecture is more efficient in the area/spl times/time product sense. In fact, it is shown that a performance improvement in excess of 80% can be achieved in certain cases.