High-speed replicating current comparators for analog convolutional decoders

This paper describes two high-speed replicating current comparators (RCCs) for use in convolutional decoders. One RCC operates asynchronously by means of a negative feedback mechanism that provides an accurate virtual ground for input current summation and comparison. This circuit requires realization in BiCMOS technology. The other RCC is synchronous and can be implemented using a digital CMOS process. Since this RCC requires positive feedback, resetting is required after each operating cycle. In addition to replicating the "winner," both types of RCCs identify the winning input by means of a digital binary output voltage. The RCCs were fabricated in a 0.8 /spl mu/m BiCMOS process and feature a maximum input signal range in excess of 200 /spl mu/A. The asynchronous RCC operates at speeds up to about 200 MHz, has a resolution of 2 /spl mu/A, and consumes 5.8 mW from a 2.8 V power supply. The synchronous RCC operates up to about 100 MHz, has a resolution of 1.2 /spl mu/A, and consumes 2.5 mW from a 3 V power supply. The measurements are compared with post-layout simulations.