Flexible implementation of a WCDMA Rake receiver

This paper presents an ASIC implementation of a WCDMA Rake receiver. The implementation is based on a FlexRake architecture that shares resources between multipath components and uses parallelism for multiple code channels. This approach facilitates the multipath allocation and improves the receiver modularity. The architecture was implemented using register-transfer-level VHDL description and logic synthesis with standard cells. Synthesis for 0.35 /spl mu/m technology resulted in 0.894 mm/sup 2/ area and 3.63 mW power consumption at 2.7 V.