I. Introduction
Thermally grown tunnel barriers serve as the basic components of devices used in low-temperature superconductor electronics (including superconducting quantum computing) and metallic single-electronics; they are also employed in spintronics. Such oxide layers are also a major candidate for the implementation of crested tunnel barriers for nonvolatile random access memories (NOVORAM) [1]. However, literature data concerning properties of these barriers are surprisingly sketchy, especially in the range of relatively high oxygen exposure, corresponding to specific zero-field conductances below , i.e., critical currents below in niobium-trilayer Josephson junctions. If we restrict our attention to nearly-room-temperature oxidation in this exposure range, we are aware of only very few publications [2] [3]–[6] where the average barrier height and physical barrier thickness have been derived from tunneling data. (The increase of temperature beyond leads to the gradual transformation of amorphous aluminum oxide into (- phase, with rather different properties [7].) Moreover, in all these works, the counter-electrode material was different from Nb; the choice of this material may affect the barrier parameters very substantially – see, e.g., [6]. Wafer Fabrication and Breakdown Parameters
Wafer # | Oxygen pressure | Oxidation time | Oxygen exposure (Pa-s) | Breakdown voltage (V) |
---|---|---|---|---|
Crest02 | 2.5 | 10 minutes | ||
Crest05 | 100 | 40 minutes | ||
Crest12 | 100 | 40 hours |
Here and in Table II below, the error bars are the r.m.s. deviations from the mean, at averaging over all measured samples from different chips; on-chip spreads are smaller. Note a narrow spread of breakdown voltages, implying high barrier quality.